Professional fields such as video surveillance, but also consumer fields such as that of cell phones, employ integrated circuits having one or more microprocessors. Often, these circuits are aimed at applications which, although very specific, are able to make use of numerous input/output interfaces.
On the one hand, these circuits often have to send and receive data in various formats which are not the one for the processor or processors. If each processor manages its own inputs/outputs, that takes all of its computation power. There is no longer any time for it to perform its application software processing. In fact, as it involves controlling the logic state of the outputs in each clock cycle, a processor does not even have the computation power necessary to manage its inputs/outputs. It therefore appears desirable for the circuit to have dedicated peripherals for managing the inputs and the outputs so as to free the processors.
On the other hand, however, these circuits, when in general use and not dedicated to an application defined during their design stage, will no doubt be required, in the course of their use, to send and receive data according to input/output protocols which are not yet known at the time of manufacture of the circuit! In this case, the provision of peripherals for managing the inputs/outputs is a problem.
A current solution implemented on general-use microprocessor or multiprocessor circuits involves implementing a large number of dedicated peripherals for managing the inputs/outputs aimed at various input/output protocols. This is a matter of providing the widest possible coverage, qualitatively and quantitatively, for the range of input/output interfaces which are liable to be used. An example of one such circuit according to the prior art can be found in an article which was presented to the ISSCC conference in February 2007 by B. Khailany et al. under the number 15.2. The article is entitled “A Programmable 512GOPS Stream Processor for Signal, Image and Video Processing”. This circuit has numerous peripherals for managing permanently wired inputs/outputs. Thus, the circuit will be permanently unsuited to an application which uses a new interface, for which no dedicated peripheral has been wired during manufacture. Moreover, an application may require the use of a given type of interface more times than there are dedicated peripherals for this type of interface. The circuit is thus permanently unsuited to such an application. Furthermore, it should not be forgotten that, in practice, most peripherals for managing inputs/outputs on such a circuit remain unused. This is because a given application uses only a limited number of interfaces among all the types of interface which are known at the time of manufacture of the circuit. Therefore, the circuit is often very bulky for no reason, since the majority of its surface holds unused peripherals.
To attempt to make up for these drawbacks, current processors use standard registers called “GPIOs”, according to the acronym for “General Purpose Inputs/Outputs”. The direction of use, whether at the input, at the output or at high impedance, is controlled by a register which can be loaded by the processor. The value of the outputs is programmed by another register, which is likewise loaded by the processor. The value of the inputs can be read by the processor. Thus, the inputs/outputs by a GPIO register are managed by the processor itself. This solution can therefore be applied only to interfaces which are sufficiently slow for the processor to be able to control them while retaining sufficient time for its application software tasks.
Another current solution is disclosed in the American patent U.S. Pat. No. 6,931,466. A low-level part of the protocol is managed by a processing processor, since some pins can be programmed as GPIOs and therefore controlled directly by the processing processor. An intermediate part of the protocol is managed by a dedicated DMA (“Direct Memory Access”) machine, the DMA machine being situated outside of the input/output peripherals. The low part of the protocol is managed by a state machine of “Pin State Machine” type, which is itself made up of a state register and a PLA (“Programmable Logic Array”). A major drawback of this solution is that a PLA is programmed by masking. Thus, even if it is possible to change the protocol by changing only a single manufacturing mask and not the whole set, it should be noted that once the circuit has been produced it is no longer possible to change the program! This solution therefore lacks flexibility and allows only fairly simple protocols to be addressed. In any case, it does not allow the processing processors to be freed completely.